I had two groups (of 3 and 4 students) present the same project back when I was teaching Digital Systems (VHDL similar to Verilog).

I could tell between who "paid for the pizza" and who could actually defend their own work but I wanted them to own up to it and be accountable for their dishonesty.

With a bit of chance, I told them to write the names of the people that worked on the project, 4 max. Those in the list will pass and those not in it would fail.

Left all 7 by themselves for an hour to deliberate. Those that didn’t work thought picking names at random would be just. Those that put in the effort wanted it to be based on merit.

Came back with a list of 3 names. Those passed. Based on merit.

Needless to say they weren’t “friends” anymore after that and I wasn’t the villain in their minds for “failing” them.

I think they learned a valuable lesson, even those that passed.

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Discussion

I’ve had a slight exposure to writing Verilog on a Field programmable gate array development board. I have forgotten everything now, but working on the board was a cool experience

How difficult is VHDL? I’ve been asked to pick up some FPGA skills for work, been debating between starting with that or verilog.