I think it’ll take 1.5 years at least to be ready for GA, so it will not be integrated in the first revisions of my products
There are also certain constraints (for a smart card, you need a UART + ISO 14443 CL interface)
I am also working with a very large SE vendor to see what I can do about making my part of the SE firmware stack auditable
Interesting.
I can’t wait to see what you come up with.
Unfortunate fact is that in the semiconductor industry there’s a lot of closed stuff that you can’t really not use, like:
- PDKs for process nodes are usually under NDA (competitive information)
- Proprietary ASIC synthesis/PNR tools
- Certain security IPs (cost to develop + patents!)
- Other IP blocks like flash
Very unfortunate… hopefully in the near-ish future this changes…
It does surprise me that theres trade secrets tho… what does surprise me is that there isn’t at least one open source option (even if it’s bad?) that could work.
Unlikely it will for PDKs, as most people do not need them (only when you want to fab a chip) and too much competitive risk
PNR tools, no one cares
For logic synthesis, there is the bunch of loosely held together tools called Yosys, which unfortunately uses ABC for logic synthesis which is garbage
IP blocks cost $$$ to develop and could involve licensing patents
