RTOS : software that manages the **time** and **resources** of a CPU

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ISR (Interrupt Service Routines) is a hardware feature, has nothing to do with the RTOS

An interrupt is a hardware mechanism used to inform the CPU that an asynchronous event has occurred

ISR is the kernel service in OS

ISR is used to handle hardware interrupt

NMI (Nonmaskable Interrupt)

provided on most microprocessors

NMI cannot be disabled, interrupt latency, response, and recovery are minimal

Interrupt : is a signal to the processor indicating an event that needs immediate attention

Micrium OS interrupt handlers (ISRs) take over when interrupts occur

The ISR saves CPU registers and calls OSIntEnter() and OSIntExit()

After the ISR, the scheduler decides which takes to run

Micrium OS has a built-in ISR : the kernel’s tick handler

ISR is provided by Micrium OS to handle interrupt from outside hardware

Critical Section of **Code**

A piece of code that can’t be interrupted

Contexts switch

Tasks switch

ROM : Read Only Memory (code space)

RAM : Random Access Memory

All it needs to do is save and restore processor registers

Semaphores have two basic operations

Pend : wait for event

Post : signal occurrence of event

Task : pend semaphore

ISR : post semaphore

Pend Operation

Decrements counter and executed waiting task

Or else moves ready task into waiting state

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Post Operation

Increments counter to signal occurrence of an event

Or else moves waiting task into ready state

A pend operation can only be performed by a task, not by an ISR

OS Services > Service APIs

Service vs API

Semaphores are used to synchronize tasks

Semaphores use a counter to track the number of events

Posting a semaphore notifies a task about an event

A semaphore pend allows a task to wait on an event

Potential problem of semaphore is priority invertion

Low priority task holds some resources which are needed by high priority task.

1. Low priority task is running and holding the key resource which is also needed by high priority task (high priority is in waiting state for an event to occur and another condition to run the high priority task is to have the key resource which is now holding by the low priority)

2. ISR occurs and the event needed by the high priority task is coming in. The high priority task begins to run, but the key resource is holding by low priority. Then high priority task releases the CPU control.

3. The OS scheduler finds a middle priority task in ready tasks list and give CPU control to middle priority task

4. Middle priority task completes and low priority task continues to run (since high priority task still waiting for the key resource which is still held by low priority task)

5. Low priority task finishes and releases the key resource. High priority task begins to run

This is priority inversion

Resource Protection

Disabling and enabling interrupts

Locking and unlocking the scheduler

Semaphores

Mutexes