also, people want shit that works
because those tasks usually can be achieved by the means of googling it and changing a few things in the code
it is a glorified lossy data compression algorithm
first of all, AI is crap at writing code, and is mostly a buzzword. second, node-based editors already exist and will achieve what you want nostr:note1fell5dd8zaux3x8gwx6tkzm5z9znswtmjsga4r20tyjyahm96hws5qdej8
not everyone wants to use a remote signer and is fine with a browser extension nostr:note16wlrvt6jwuzc5vh4wpd3elvak47c7g9fc75vrhl8h6znmn7c2d5qr8p9u2
#0 $0
#1 -$800 and a cow
#2 $200
#3 -$900 and a cow
#4 $400
is your node obese? check with this simple test nostr:note19dmh50dlf82pynuxnknzxgm0pk39udjphxqk5zuuz7s9fzlymzms43n3ur
t = āESC :q ENTERā š
nostr:npub18ams6ewn5aj2n3wt2qawzglx9mr4nzksxhvrdc4gzrecw7n5tvjqctp424 add āalias rm=vimā just in case to your .bashrc
> to be a real person for engagement purposes
So their content can be seen, but their reactions, renotes, I thinks zaps too etc will get ignored
semisol.83
WPA3-Enteprise means you could route different users (guest/yourself) to different VLANs, and also if you have multiple guests, give them different credentials. You can also expire credentials after some time, etc.
SimpleX works too though
I don't have working DMs yet sorry. I can drop a simplex link if you're interested
https://www.vaughnnugent.com/resources/software/modules/noscrypt-issues?id=58
That was what I DMed you about⦠:)
Do you use Signal or TG or Matrix instead?
What I really want to do is WPA3-Enterprise + an e-ink display with rotating credentials.
Also, itās less the language more concepts. But a lot more things support Verilog afaik.
Verilog is like C but VHDL is some abomination that is like C++ and Java
You should absolutely use FuseSoC. It makes it *very* easy to interface with whatever tools of your choice + package management of sorts.
Currently developing for an iCE40 UP5K with Verilog, so Yosys for synthesis and nextpnr/icestorm for the FPGA bitstream generation.
iCE40 UltraPlus is nice as they are pretty cheap, they have 1024Kbit in 4 large RAM blocks, and a REād open source toolchain that works great.
If you insist on using VHDL there is this: https://github.com/ghdl/ghdl-yosys-plugin
I am writing HDL⦠it is good except when it is not š¤£
formal verification somewhat helps
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